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Python Officially Elevates RISC-V to Tier 3 Support Status.
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Python Grants Official Tier 3 Support Status to RISC-V Architecture
Stan Ulbrych, one of the core maintainers of the Python programming language, has officially announced that the RISC-V processor architecture has been elevated to Tier 3 support status. This milestone ensures that Linux systems running on RISC-V hardware will receive synchronized, day-zero releases alongside other major computing platforms for future Python versions.
Python manages platform stability across three distinct support tiers:
Tier 1 (Primary Architectures): The most critical tier. If a build fails on a Tier 1 platform, releases are immediately blocked, and any breaking patch must be reverted right away.
Tier 2 (Secondary Architectures): Stable platforms requiring reliable builds. If a patch breaks a Tier 2 platform, it must be fixed or reverted within 24 hours, and new Python versions will not ship until the issue is resolved.
Tier 3 (Experimental/Community Architectures): Platforms monitored by continuous build systems (buildbots), but without strict release-blocking promises. If a build breaks, releases can still proceed while maintainers work on asynchronous fixes. Other Tier 3 platforms include iOS on arm64, Android on x86-64, WebAssembly (WASM), PowerPC, and FreeBSD on x86-64.
This milestone was made possible through sponsorship from the RISE Project (RISC-V Software Ecosystem), which donated dedicated RISC-V hardware to host buildbots within Python's continuous integration pipeline. Following this milestone, Ulbrych plans to continue pushing RISC-V toward Tier 2 support status.
Why is RISC-V support so important to the software industry? Unlike proprietary architectures controlled by various companies (e.g., x86 by Intel/AMD or ARM by Arm Ltd.), RISC-V is an open, standard instruction set architecture (ISA). As global tech companies and research institutions build custom AI chips, embedded microcontrollers, and cloud servers on RISC-V, high-level Python support enables developers to run data analytics, web services, and automated scripts directly on open hardware.
The RISE (RISC-V Software Ecosystem) alliance brings together industry leaders—including Google, Red Hat, Meta, Nvidia, and Qualcomm—to support the software side of open hardware. Hardware requirements alone are useless without software compatibility. Funding support for buildbot servers for high-level programming languages like Python bridges the gap between early hardware production and commercial software availability.
Moving from Tier 3 to Tier 2 is necessary to prove the long-term reliability of buildbot, minimizing transient test failures. This also ensures a dedicated core team of developers committed to maintaining the platform throughout multiple major Python releases. As RISC-V hardware becomes more prevalent in developer workstations and server farms, achieving Tier 2 will provide hardware developers with assurance that Python will not compromise their platform during development cycles.
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Python Grants Official Tier 3 Support Status to RISC-V Architecture
Stan Ulbrych, one of the core maintainers of the Python programming language, has officially announced that the RISC-V processor architecture has been elevated to Tier 3 support status. This milestone ensures that Linux systems running on RISC-V hardware will receive synchronized, day-zero releases alongside other major computing platforms for future Python versions.
Python manages platform stability across three distinct support tiers:
Tier 1 (Primary Architectures): The most critical tier. If a build fails on a Tier 1 platform, releases are immediately blocked, and any breaking patch must be reverted right away.
Tier 2 (Secondary Architectures): Stable platforms requiring reliable builds. If a patch breaks a Tier 2 platform, it must be fixed or reverted within 24 hours, and new Python versions will not ship until the issue is resolved.
Tier 3 (Experimental/Community Architectures): Platforms monitored by continuous build systems (buildbots), but without strict release-blocking promises. If a build breaks, releases can still proceed while maintainers work on asynchronous fixes. Other Tier 3 platforms include iOS on arm64, Android on x86-64, WebAssembly (WASM), PowerPC, and FreeBSD on x86-64.
This milestone was made possible through sponsorship from the RISE Project (RISC-V Software Ecosystem), which donated dedicated RISC-V hardware to host buildbots within Python's continuous integration pipeline. Following this milestone, Ulbrych plans to continue pushing RISC-V toward Tier 2 support status.
Why is RISC-V support so important to the software industry? Unlike proprietary architectures controlled by various companies (e.g., x86 by Intel/AMD or ARM by Arm Ltd.), RISC-V is an open, standard instruction set architecture (ISA). As global tech companies and research institutions build custom AI chips, embedded microcontrollers, and cloud servers on RISC-V, high-level Python support enables developers to run data analytics, web services, and automated scripts directly on open hardware.
The RISE (RISC-V Software Ecosystem) alliance brings together industry leaders—including Google, Red Hat, Meta, Nvidia, and Qualcomm—to support the software side of open hardware. Hardware requirements alone are useless without software compatibility. Funding support for buildbot servers for high-level programming languages like Python bridges the gap between early hardware production and commercial software availability.
Moving from Tier 3 to Tier 2 is necessary to prove the long-term reliability of buildbot, minimizing transient test failures. This also ensures a dedicated core team of developers committed to maintaining the platform throughout multiple major Python releases. As RISC-V hardware becomes more prevalent in developer workstations and server farms, achieving Tier 2 will provide hardware developers with assurance that Python will not compromise their platform during development cycles.
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