Huawei Outlines LogicFolding Architecture to Achieve 1.4nm Equivalence and Rewrite Moore’s Law.
Huawei Unveils "LogicFolding" and Tau Scaling Law to Bypass Moore’s Law Limitations In a major technical presentation at the IEEE International Symposium on Circuits and Systems (ISCAS), Huawei introduced a radical paradigm shift in semiconductor design labeled "LogicFolding." The newly unveiled framework is engineered specifically to counteract the stagnation of Moore's Law, which historically dictated that the number of transistors on a microchip doubles roughly every two years. As physical limits make traditional silicon shrinking increasingly unviable, Huawei’s new design methodology pivots away from pure transistor density. Instead, it focuses heavily on minimizing data propagation delay a principle the tech giant defines as "Tau ( τ ) Scaling Law." The Four Pillars of Tau Scaling Law The Tau Scaling Law framework optimizes chip performance across four interconnected architectural layers: Device Level: Re-engineering physical components to dras...