MediaTek Validates Dual-Source Advanced Packaging, Supporting Both TSMC CoWoS and Intel EMIB for Custom AI SiliconIn a strategic move to diversify its manufacturing ecosystem, MediaTek has officially announced full architectural support for next-generation advanced packaging technologies from both TSMC and Intel. This positioning establishes MediaTek as one of the elite few fabless chip designers capable of deploying dual-platform architectures specifically leveraging TSMC’s CoWoS and Intel’s EMIB platforms customized entirely to sovereign client infrastructure demands.
Deconstructing the Interconnect Technologies: CoWoS vs. EMIB
Advanced packaging has become the primary bottleneck and performance multiplier in high-performance computing (HPC) and artificial intelligence:
TSMC CoWoS (Chip-on-Wafer-on-Substrate): TSMC’s signature 2.5D packaging standard. CoWoS integrates multiple silicon dies onto a single passive silicon interposer, serving as the foundational architectural backbone for industry-dominant hardware like NVIDIA’s AI accelerators.
Intel EMIB (Embedded Multi-die Interconnect Bridge): Intel’s proprietary packaging methodology. Instead of utilizing a massive, costly silicon interposer across the entire substrate, EMIB relies on tiny embedded silicon bridges placed precisely under the edges of die-to-die connections, offering a highly cost-efficient alternative for high-density routing.
The Pivot to Custom AI Hardware and A14 Silicon Roadmap
This multi-packaging flexibility comes as MediaTek undergoes a major structural revenue transformation. While historically reliant on standard smartphone application processors (APs), the company is locking in exponential revenue growth from its Custom AI ASIC (Application-Specific Integrated Circuit) enterprise division.
Furthermore, MediaTek revealed that it has successfully initiated tape-out testing for prototype silicon built on TSMC’s cutting-edge A14 (1.4nm-class) process node. This next-generation architecture is slated to enter high-volume mainstream production by 2028.
The chip industry has currently reached a point of no return due to Moore's Law. Making monolithic dies progressively smaller is difficult and costly. The world has therefore shifted to the era of chiplets, where multiple small chips (such as processors and HBM memory chips) are assembled like Lego bricks. Therefore, "advanced packaging" (chip packaging technology) has become the new battleground in determining which AI chip offers faster processing and data transfer speeds. MediaTek's support for both Intel and TSMC gives them a significant competitive advantage.
The global market currently faces a CoWoS capacity bottleneck, where TSMC's CoWoS production capacity is insufficient to meet demand, leading to a shortage of AI chips. MediaTek's announcement of its ability to design chips that can switch to Intel's EMIB (Entire Integrated Minute Chip) allows them to offer large enterprise customers (such as cloud giants and hyperscalers) the option of "if TSMC's production queue is full, we can immediately move chip packaging to Intel's foundry." This cleverly solves the supply chain bottleneck and enhances their bargaining power.
Initially, MediaTek was primarily known for manufacturing Dimensity chips in mid-to-high-end smartphones. However, changing revenue figures and its move to collaborate on testing A14 (1.4nm) architecture chips demonstrate that MediaTek is directly challenging custom ASIC giants Broadcom and Marvell for a share of the lucrative data center AI accelerator market, which boasts significantly higher profit margins than mobile chips.
NASA 3-Mission Plan to Dominate the Moon South Pole in 2026.
Source: Reuters
MediaTek Validates Dual-Source Advanced Packaging, Supporting Both TSMC CoWoS and Intel EMIB for Custom AI SiliconIn a strategic move to diversify its manufacturing ecosystem, MediaTek has officially announced full architectural support for next-generation advanced packaging technologies from both TSMC and Intel. This positioning establishes MediaTek as one of the elite few fabless chip designers capable of deploying dual-platform architectures specifically leveraging TSMC’s CoWoS and Intel’s EMIB platforms customized entirely to sovereign client infrastructure demands.
Deconstructing the Interconnect Technologies: CoWoS vs. EMIB
Advanced packaging has become the primary bottleneck and performance multiplier in high-performance computing (HPC) and artificial intelligence:
TSMC CoWoS (Chip-on-Wafer-on-Substrate): TSMC’s signature 2.5D packaging standard. CoWoS integrates multiple silicon dies onto a single passive silicon interposer, serving as the foundational architectural backbone for industry-dominant hardware like NVIDIA’s AI accelerators.
Intel EMIB (Embedded Multi-die Interconnect Bridge): Intel’s proprietary packaging methodology. Instead of utilizing a massive, costly silicon interposer across the entire substrate, EMIB relies on tiny embedded silicon bridges placed precisely under the edges of die-to-die connections, offering a highly cost-efficient alternative for high-density routing.
The Pivot to Custom AI Hardware and A14 Silicon Roadmap
This multi-packaging flexibility comes as MediaTek undergoes a major structural revenue transformation. While historically reliant on standard smartphone application processors (APs), the company is locking in exponential revenue growth from its Custom AI ASIC (Application-Specific Integrated Circuit) enterprise division.
Furthermore, MediaTek revealed that it has successfully initiated tape-out testing for prototype silicon built on TSMC’s cutting-edge A14 (1.4nm-class) process node. This next-generation architecture is slated to enter high-volume mainstream production by 2028.
The chip industry has currently reached a point of no return due to Moore's Law. Making monolithic dies progressively smaller is difficult and costly. The world has therefore shifted to the era of chiplets, where multiple small chips (such as processors and HBM memory chips) are assembled like Lego bricks. Therefore, "advanced packaging" (chip packaging technology) has become the new battleground in determining which AI chip offers faster processing and data transfer speeds. MediaTek's support for both Intel and TSMC gives them a significant competitive advantage.
The global market currently faces a CoWoS capacity bottleneck, where TSMC's CoWoS production capacity is insufficient to meet demand, leading to a shortage of AI chips. MediaTek's announcement of its ability to design chips that can switch to Intel's EMIB (Entire Integrated Minute Chip) allows them to offer large enterprise customers (such as cloud giants and hyperscalers) the option of "if TSMC's production queue is full, we can immediately move chip packaging to Intel's foundry." This cleverly solves the supply chain bottleneck and enhances their bargaining power.
Initially, MediaTek was primarily known for manufacturing Dimensity chips in mid-to-high-end smartphones. However, changing revenue figures and its move to collaborate on testing A14 (1.4nm) architecture chips demonstrate that MediaTek is directly challenging custom ASIC giants Broadcom and Marvell for a share of the lucrative data center AI accelerator market, which boasts significantly higher profit margins than mobile chips.
NASA 3-Mission Plan to Dominate the Moon South Pole in 2026.
Source: Reuters
Comments
Post a Comment